The Altera EPM7032S CPLD bitstream format

Introduction

This page is an inofficial documentation for Altera's EPM7032S CPLD bitstream format. It is presented here in the hope that at some point the information here may be sufficient to allow implementation of third-party software to support this programmable logic device, namely in the context of SymbiFlow.

This is an automatically generated page. The corresponding generator can be found here.

The official way to generate bitstreams for this device is to use Altera Quartus-II. Quartus-II produces POF files as output, which contain the raw bitstream alongside some metadata, and SVF files for JTAG programming. For software tools handling POF files, see libalterpof.

The official device family datasheet can be found here.

Disclaimer

Keep in mind that this is a third-party specification. Therefore it may be incorrect, inaccurate or incomplete. There may be no technical measure present in your device preventing you from loading a flawed bitstream. If you use the information on this page to program your device, you may permanently damage or destroy your hardware. The authors expressly disclaim any liability for damages arising from any kind of usage of this document.

Bitstream overview

The bitstream for the EPM7032S consists of 15033 bits in total.

	Function	from bit	to bit (incl.)	Bit count	Composed of
1	Product term configuration	1	14080	14080	2 logic array blocks x 16 macrocells x 5 product terms x (36x2 + 16) selectable input signals x 1 bit per signal
2	Macrocell logic configuration	14081	14496	416	2 logic array blocks x 16 macrocells x 13 bits per macrocell
3	PIA-to-LAB routing	14497	14784	288	2 logic array blocks x 36 signals from global routing pool x 4 choices per router x 1 bit per choice
4	Output buffer tri-state control	14785	14814	30	6 global output enable signals x 5 bits per output enable
5	Pin configuration	14815	15006	192	32 pins x 6 bits per block
6	Unkown function	15007	15017	11
7	Usercode	15018	15033	16

Product terms

The device contains 2 Logic Array Blocks (LABs), each containing 16 macrocells. Every macrocell can use between 0 and 5 product terms to calculate a sum-of-products. Each of those product terms can use up to 44 different input signals choosable from 88 nets to calculate a product. To enable the inclusion of a net into a product term, the corresponding bit in the bitstream must be toggled: A '1' represents a disregarded signal, a '0' appends the signal to the product. Therefore, each product term is configured by 88 bits and 14080 bits of the bitstream configure all the device's product terms. The product term configuration bits appear clustered in the bitstream and in the following order: product term 1 first - 5 last, macrocell 1 first - 16 last, LAB A first - B last. Within one product term the earlier 72 bits switch global signals: 36 global signals are routed to each LAB from the PIA. Two consecutive bits switch one of those global signals - the first bit non-inverted, the second inverted. Another 16 bits switch regional foldback signals from outputs of macrocells within the same LAB.

Macrocell configuration

In this context by macrocell configuration it is referred to everything configurable between product terms and macrocell input/output signal. The macrocell bits are expected to configure:

Select product terms: Probably five bits, one per product term
Select logic type: Combinatorial (latch) or flip-flop (at least one bit)
Select D-FF clock signal: GCLK1 or GCLK2 or a product term (at least two bits)
Select D-FF enable signal: None or OE1 or OE2 or product term? (two bits?)
Select D-FF clear signal: None or GCLR or product term (two bits?)
Enable parallel expander input (one bit?)

It appears, 13 bits configure one macrocell. With 2 LABs this makes for 416 bits (52 bytes) in total for macrocell configuration.

Preliminary configuration bit order

It seems, the macrocell configuration bits appear in the following order in the bitstream:

PT1E

PT2E

PT3E

PT4E

PT5E

CLKS

CLRS

???

DFFE

GCLKS

PT1E: Enable inclusion of product term 1 in the sum: If PTxE is 0, then the product term is connected to the OR gate. If PTxE is 1, then the product term is disregarded.
PT2E: Enable inclusion of product term 2 in the sum
PT3E: Enable inclusion of product term 3 in the sum
PT4E: Enable inclusion of product term 4 in the sum
PT5E: Enable inclusion of product term 5 in the sum
CLKS: Select the macrocell's flip-flop clock source: If CLKS is 0, then a global clock is used. If CLKS is 1, then the macrocell's product term 4 result is used.

Selection of global signals for a LAB (PIA-to-LAB routing)

Every LAB can use 36 global signals by routing them to the LAB from the PIA. A global signal is selected by enabling the corresponding switch/multiplexer: One bit switches one signal. A '1' bit disables a PIA signal, a '0' bit enables it. Caveat: Enabling multiple switches for one LAB signal may permanently damage the device.
Every LAB signal can be selected from 4 choices. With one bit per choice this makes for 144 bits per LAB and 288 bits (36 bytes) in total for PIA to LAB routing configuration. Assuming that every switch/multiplexer selects a different PIA signal, a maximum of 144 PIA signals is routable to one LAB.

Selection of output enable signals

Every I/O pin can select one of six global signals as output enable signal (tri-state control signal).

The output enable signals are usually active high: When the signal of is low, the pin is in high-impedance state. When it is high, the pin assumes the logic level defined by the output of the corresponding macrocell. It is also possible to use an inverted output enable signal and thus realize active-low output enable function.

A total of 6 global output enable signals are available, which somehow can be chosen from PIA signals, probably similar to the way signals are routed to a LAB: One bit selects one PIA signal as OE signal. A '1' bit indicates a disregarded signal, a '0' bit selects a PIA signal as output enable signal. Caveat: Enabling multiple switches for one LAB signal may permanently damage the device.

It appears, that 4 bits select, which PIA signal is used as global output enable signal. A 5th bit indicates, whether the signal is used non-inverted or inverted.

I/O configuration

6 bits configure one I/O block(?). With 32 I/O blocks this would make for 192 bits (24 bytes) in total for I/O configuration.

OES

SRS

Bits 1,2,3: Output enable select
Bit 4: Slew rate, 0=fast, 1=slow
Bit 5,6: ?

Usercode

A 16-bit user electronic signature (usercode) is stored in the bitstream. It occupies it's last 16 bits. It's bits and bytes are in reversed order (additionally to the reversed order that bits are stored in a POF file).

Example

Last 3 bytes of the bitstream payload in the POF file	0x9a	0x57	0x01
	1001 1010	0101 0111	0000 0001
Bitstream bit order	0101 1001	1110 1010	1000 0000
	0101 1001 1110 1010 1000 0000
Last 16 bits of the bitstream	1011 0011 1101 0101
Inverted bit order	1010 1011 1100 1101
Usercode	0xABCD

Unidentified functions

The yet unidentified bits of the bitstream are expected to configure:

Product selection for sum-of-products term
XOR second input signal selection
Cascading from previous/to next macrocell
Flipflop vs. latch selection/mux
FF clock signal selection
FF enable signal selection
Configuration of feedback from macrocell to PIA
I/O Output Enable (OE) signal selection
I/O type selection: push-pull vs. open collector
I/O slew rate control: slow vs. fast
Usercode
JTAG enable/disable

Bit table

LAB A

Macrocell 1

PT1

PT2

PT3

PT4

PT5

Macrocell 2

PT1

PT2

PT3

PT4

PT5

Macrocell 3

PT1

PT2

PT3

PT4

PT5

Macrocell 4

PT1

PT2

PT3

PT4

PT5

Macrocell 5

PT1

PT2

PT3

PT4

PT5

Macrocell 6

PT1

PT2

PT3

PT4

PT5

Macrocell 7

PT1

PT2

PT3

PT4

PT5

Macrocell 8

PT1

PT2

PT3

PT4

PT5

Macrocell 9

PT1

PT2

PT3

PT4

PT5

Macrocell 10

PT1

PT2

PT3

PT4

PT5

Macrocell 11

PT1

PT2

PT3

PT4

PT5

Macrocell 12

PT1

PT2

PT3

PT4

PT5

Macrocell 13

PT1

PT2

PT3

PT4

PT5

Macrocell 14

PT1

PT2

PT3

PT4

PT5

Macrocell 15

PT1

PT2

PT3

PT4

PT5

Macrocell 16

PT1

PT2

PT3

PT4

PT5

LAB B

Macrocell 17

PT1

PT2

PT3

PT4

PT5

Macrocell 18

PT1

PT2

PT3

PT4

PT5

Macrocell 19

PT1

PT2

PT3

PT4

PT5

Macrocell 20

PT1

PT2

PT3

PT4

PT5

Macrocell 21

PT1

PT2

PT3

PT4

PT5

Macrocell 22

PT1

PT2

PT3

PT4

PT5

Macrocell 23

PT1

PT2

PT3

PT4

PT5

Macrocell 24

PT1

PT2

PT3

PT4

PT5

Macrocell 25

PT1

PT2

PT3

PT4

PT5

Macrocell 26

PT1

PT2

PT3

PT4

PT5

Macrocell 27

PT1

PT2

PT3

PT4

PT5

Macrocell 28

PT1

PT2

PT3

PT4

PT5

Macrocell 29

PT1

PT2

PT3

PT4

PT5

Macrocell 30

PT1

PT2

PT3

PT4

PT5

Macrocell 31

PT1

PT2

PT3

PT4

PT5

Macrocell 32

PT1

PT2

PT3

PT4

PT5

LAB A

Macrocell 1

LAB A

Macrocell 2

LAB A

Macrocell 3

LAB A

Macrocell 4

LAB A

Macrocell 5

LAB A

Macrocell 6

LAB A

Macrocell 7

LAB A

Macrocell 8

LAB A

Macrocell 9

LAB A

Macrocell 10

LAB A

Macrocell 11

LAB A

Macrocell 12

LAB A

Macrocell 13

LAB A

Macrocell 14

LAB A

Macrocell 15

LAB A

Macrocell 16

LAB B

Macrocell 17

LAB B

Macrocell 18

LAB B

Macrocell 19

LAB B

Macrocell 20

LAB B

Macrocell 21

LAB B

Macrocell 22

LAB B

Macrocell 23

LAB B

Macrocell 24

LAB B

Macrocell 25

LAB B

Macrocell 26

LAB B

Macrocell 27

LAB B

Macrocell 28

LAB B

Macrocell 29

LAB B

Macrocell 30

LAB B

Macrocell 31

LAB B

Macrocell 32

LAB A

PIA-Mux 1-36

LAB B

PIA-Mux 37-72

Unknown function

I/O block 1

I/O block 2

I/O block 3

I/O block 4

I/O block 5

I/O block 6

I/O block 7

I/O block 8

I/O block 9

I/O block 10

I/O block 11

I/O block 12

I/O block 13

I/O block 14

I/O block 15

I/O block 16

I/O block 17

I/O block 18

I/O block 19

I/O block 20

I/O block 21

I/O block 22

I/O block 23

I/O block 24

I/O block 25

I/O block 26

I/O block 27

I/O block 28

I/O block 29

I/O block 30

I/O block 31

I/O block 32

Extra bits

Usercode

Bits 16-1